OLD Design Verification Engineer

OLD Design Verification Engineer Overview

This is an opportunity to join a highly regarded company working on advanced silicon technology for AI-focused computing. The role sits within a world-class silicon engineering environment and offers the chance to contribute to products that are helping shape the future of AI hardware and software. The business is backed by a major investor with a strong commitment to ongoing support for innovative AI companies, making this a particularly exciting setting for verification engineers who want to work on cutting-edge technology.

The position is based in Bristol, England, and the package includes a competitive base salary together with bonus potential. The employer also highlights a flexible working approach and a strong overall benefits package.

What you will do

• Take responsibility for verification work within the wider verification team, supporting the delivery of complex silicon projects.
• Develop and manage verification plans, define specifications, and work through the closure of functional coverage.
• Maintain strong communication between different sites and teams so that verification activity stays aligned and coordinated.
• Work closely with architects by feeding back verification findings and helping refine technical decisions.
• Generate tests, analyse failures, and carry out detailed diagnosis and triage to identify underlying issues.
• Contribute to the development and upkeep of shared verification infrastructure used across the team.

What the employer is looking for

• Prior verification engineering experience in a relevant sector is required.
• Applicants should bring evidence of leadership capability and solid planning skills.
• You need to be comfortable working across multiple teams and programming languages to trace and resolve deep, complex technical problems.
• Experience with verification in CPU and/or ASIC environments is essential.
• Practical knowledge of SystemVerilog, Python, C++, and Linux is expected.
• Experience with UVM and SVA is relevant and desirable for the role.
• Exposure to LLVM, GCC, SGE or other distributed resource management systems, as well as XML and XPath/XSLT, would be beneficial.
• The company welcomes both traditional UVM-based verification engineers and candidates with software verification experience using Python and C/C++.

Package and benefits

• Competitive salary with bonus opportunities.
• Flexible working arrangements.
• Generous holiday allowance.
• Private medical insurance.
• Health cash plan.
• Dental insurance.
• Pension contributions matched by the employer up to 5%.
• Life assurance cover.
• Income protection cover.

How to apply

Interested candidates are invited to apply now. For further information, the contact named on the advert is Rachel Mason, Business Manager in Semiconductors at IC Resources, who can be reached by phone or email.

Degree Requirement: Not Specified

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