Design Verification Engineer

Design Verification Engineer Overview

This is an opportunity to join a highly regarded silicon engineering organisation working on advanced AI compute hardware and software. The role sits within a world-class verification team contributing to products that are described as setting the benchmark for made-for-AI compute. The company is backed by significant and ongoing investment from a major supporter of innovative AI businesses, and the position offers the chance to help develop technology intended to have a major impact on the future.

What you will do

• Take part in verification work within a dedicated verification team supporting silicon development.
• Plan verification tasks, define the verification strategy, and work through to closure of functional coverage.
• Keep communication flowing effectively between different sites and teams so that verification activity stays aligned.
• Give architects feedback based on verification results, coverage progress, and issues discovered during testing.
• Develop and execute tests, then investigate any failures and carry out diagnosis and triage to identify root causes.
• Help create, improve, and maintain shared verification infrastructure used across the team.
• Contribute to verification efforts in CPU and ASIC environments, using both UVM-based approaches and software-oriented verification methods where appropriate.
• Apply programming and scripting skills in tools and languages such as Python, C/C++, and SystemVerilog to support verification tasks.

What the employer is looking for

• Prior verification experience gained in a relevant industry setting.
• Evidence of leadership ability and strong planning skills in a verification context.
• The ability to collaborate across teams and across different programming languages to uncover the root cause of difficult and deeply technical issues.
• Experience with the verification process in CPU and/or ASIC development programmes.
• Working knowledge of SystemVerilog, Python, C++, and Linux.
• Experience using UVM and SVA.
• Exposure to LLVM, GCC, and SGE or similar distributed resource management systems is beneficial.
• Knowledge of XML and XPath/XSLT is included in the technical profile.
• Software verification experience using Python and C/C++ is welcomed alongside traditional UVM verification expertise.

Package and working environment

• Competitive salary.
• Equity or stock-based elements included in the overall package.
• Flexible working arrangements.
• Substantial annual leave allowance.
• Private medical cover.
• Health cash plan.
• Dental insurance.
• Pension scheme with employer matching up to 5%.
• Life assurance.
• Income protection.

The role is based in Bristol, England. Interested candidates are invited to apply now or contact Rachel Mason at IC Resources for further information.

How to apply

Applicants can submit an application through the job advert using the Apply Now option. The page also provides contact details for Rachel Mason, Business Manager in Semiconductors, for anyone who would like to discuss the opportunity further before applying.

Degree Requirement: Not Specified

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