Physical Design Engineer

Physical Design Engineer Overview

An established technology business in Cambridge is looking to add a Physical Design Engineer to its growing engineering group. The company develops a range of high-volume computing and embedded products, and this hire is being made because the team continues to expand. The role offers the chance to work in a highly collaborative environment and to contribute throughout the full chip development process, starting from early design work and continuing through silicon delivery and product release.

The engineering team is described as relatively small, which means the successful candidate will gain broad exposure across the development flow and have a real opportunity to influence the direction and quality of the products being built. This is positioned as a strong opportunity for someone who wants technically challenging work, close teamwork, and visible impact.

What you will do

• Take ownership of the physical implementation flow from the netlist stage through to final GDSII output.
• Build floorplans and develop power plans for ASIC or SoC designs.
• Carry out placement, optimisation, clock tree synthesis, routing, and closure of physical verification issues.
• Work on timing closure and perform static timing analysis to ensure the design meets required performance targets.
• Apply logic synthesis, equivalence checking, and place-and-route methods as part of the implementation process.
• Support the wider chip development lifecycle, contributing from the earliest design phases through to silicon delivery and product launch.
• Collaborate with a compact engineering team and communicate effectively with colleagues across different technical disciplines.
• Help deliver complex semiconductor products where individual engineering input has a direct effect on the final outcome.

What the employer is looking for

• A strong academic foundation in Electronics, Electrical Engineering, or a similar discipline.
• At least two years of industry experience in Physical Design or Physical Implementation.
• Solid practical knowledge of modern ASIC implementation flows and the associated methodologies.
• Direct experience with the complete physical implementation process, including movement from netlist to GDSII.
• Hands-on familiarity with floorplanning, power planning, placement, optimisation, clock tree synthesis, routing, and physical verification closure.
• Experience with timing closure and static timing analysis.
• Knowledge of logic synthesis, equivalence checking, and place-and-route techniques.
• Background working on complex ASIC or SoC designs in advanced semiconductor settings.
• Good communication skills and the ability to work well in cross-functional engineering teams.

Why this role stands out

• Competitive base pay together with additional benefits.
• The opportunity to join a company with a strong engineering-led culture.
• Work on challenging technical products with substantial scope for learning and development.
• Join a close-knit team where your contribution will be noticed and will directly affect product development.
• Broader exposure to the full chip lifecycle than is often available in larger organisations.

How to apply

Interested candidates are invited to apply through the recruiter’s application process. The posting also provides direct contact details for Jordan Browne, who handles ASIC, verification, and physical design roles, and encourages candidates to get in touch for more information about this opening or other Physical Design opportunities across the UK and Europe.

The page also includes an option to request a call or submit a CV as part of the application process.

Degree Requirement: Not Specified

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