DFT Engineer

DFT Engineer Overview

This opportunity is for a design-for-test engineer to join a well-funded British AI semiconductor company in London. The business is developing next-generation accelerator hardware aimed at tackling the growing performance and efficiency demands of modern AI computing. The team is building a sophisticated AI accelerator architecture intended to push high-performance silicon forward, and the new hire will help deliver a scalable, production-ready DFT solution for a large multi-core AI accelerator ASIC.

The role offers the chance to work across scan implementation, ATPG, memory testing, and silicon bring-up, while collaborating closely with engineers from architecture, RTL, physical design, product engineering, and test. It is positioned as a strong development opportunity for someone who wants to deepen their DFT expertise while contributing to advanced, leading-edge silicon.

What you will do

• Help shape the DFT approach for a complex AI accelerator system-on-chip with multiple processing cores.
• Bring DFT methods and tools into the wider ASIC design and delivery flow.
• Implement scan insertion, scan compression, and the associated test circuitry needed for production-quality test coverage.
• Create ATPG patterns, then analyse and debug them to improve structural fault coverage.
• Support MBIST work for large embedded memory arrays on the chip.
• Work with physical design engineers to ensure scan chains are implemented robustly and timing closure is achieved.
• Develop scripts and automation to streamline DFT tasks and improve engineering efficiency.
• Assist with silicon bring-up, manufacturing test, and post-silicon debugging activities.
• Partner with product and test engineering teams to help with ATE bring-up, production test execution, and yield improvement efforts.

What the employer is looking for

• A degree in electronic engineering, computer engineering, or a similar discipline.
• Experience in DFT, digital IC design, or ASIC development.
• A good working understanding of scan architecture, ATPG, MBIST, and digital test methods.
• Familiarity with standard industry EDA tools.
• Programming or scripting ability in Python, Tcl, or comparable languages.
• A problem-solving mindset suited to technically challenging work on large-scale ASICs.
• Someone who works well with others across different engineering disciplines.
• Strong attention to detail and an interest in building deeper knowledge of design-for-test within a high-performing team.

Why this role stands out

• You will work on innovative AI silicon with clear real-world relevance.
• The company offers share options alongside a base salary and an overall compensation package described as excellent.
• You will gain exposure to the full ASIC lifecycle, from architecture through to silicon bring-up.
• You will collaborate with experienced engineers across hardware, software, and systems disciplines.
• The role gives you ownership of meaningful technical challenges while supporting ongoing career growth.
• The environment is described as highly collaborative and focused on engineering excellence.

How to apply

If you want to learn more, the recruiter invites interested candidates to get in touch in confidence for further details. Applications can be made through the Apply Now route on the listing, and the contact named on the page is Rachel Mason, Business Manager for Semiconductors at IC Resources.

The listing is for London, England.

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Degree Requirement: Bachelor’s

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