Senior DFT Engineer

Senior DFT Engineer Overview

This opportunity is for an experienced Senior DFT Engineer to join a growing ASIC team in Cambridgeshire. The role sits within a small, adaptable group that works across the full silicon delivery chain, from early specification and design through verification, implementation, ATE testing, and qualification. It is a hands-on position for someone who wants to help bring next-generation ASIC products into production while working in a collaborative environment.

The team is responsible for the complete silicon flow, so the successful engineer will have exposure to a broad range of technical activities rather than a narrow specialist function. The role focuses on designing, introducing, and validating DFT solutions for upcoming ASIC designs, with an emphasis on maintaining the quality required for high-volume shipping products. The work will involve using advanced DFT techniques to improve test coverage, control cost, and support efficient time-to-market.

What you will do

• Develop and put into practice DFT strategies across chip, subsystem, and IP levels.
• Choose between structural and functional test approaches in a pragmatic way, making sensible trade-offs to achieve the best overall outcome.
• Work with Tessent DFT tool flows to add MBIST, EDT, SSN, scan control through IJTAG, and IP test support using ICL and PDL.
• Apply these flows in both flat and hierarchical design contexts.
• Validate DFT structures and investigate any problems that arise during verification or debug.
• Support DFT implementation through to sign-off, including the creation of timing constraints.
• Resolve issues related to timing, power, and formal equivalence as part of the closure process.
• Contribute to the wider ASIC team effort by engaging in multiple stages of product delivery, not just DFT in isolation.

What the employer is looking for

• A degree in electronic engineering, computer science, or a similar discipline.
• At least five years of industry experience in DFT engineering.
• Proven experience with IC development flows.
• Strong working knowledge of Tessent DFT tools.
• A solid understanding of DFT issues in complex IP, including on-chip clocking.
• Practical experience with ATPG, MBIST, and simulation debug.
• Experience handling UPF-related issues.
• Strong scripting ability, especially in TCL.
• The ability to work effectively in a small, versatile team and contribute across the full product lifecycle.

Package and location

• The role is based in Cambridgeshire, England.
• Salary is competitive and will depend on experience.
• Benefits include private medical insurance.
• A company pension is also provided.

How to apply

Interested candidates are invited to send their CV and suggest a time for an initial conversation with the recruiter. The contact named on the page is Ane at IC Resources. The posting also notes that priority will be given first to applicants already based in the UK, and then to candidates from the EU.

Additional context

This is a specialist ASIC/verification-focused opportunity for someone who enjoys technical ownership, close collaboration, and working on cutting-edge silicon development. The position is suited to a senior engineer who can contribute immediately to DFT planning, implementation, debug, and sign-off within a production-oriented environment.

Degree Requirement: Bachelor’s

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